Optimizing Interpreters for Processors with Branch Target Buffers

Interpreters designed for efficiency execute a huge number of indirect branches and can spend more than half of the execution time in indirect branch mispredictions. Branch target buffers are the best widely available form of indirect branch prediction; they produce 50%–100% mispredictions for existing interpreters. In this paper we investigate three methods for improving the prediction accuracy of interpreters: replicating virtual machine (VM) instructions, combining sequences of VM instructions into superinstructions, and using separate dispatch branches for the two outcomes of conditional VM machine branches. In their extreme form these techniques eliminate all mispredictions except those caused by VM-level indirect branches. Applying these techniques in a more conservative way reduces the mispredictions to about 20%. We have measured speedups by factors of 1.75–3.16 on current processors from these techniques.